1. Field of the Invention
This invention relates to a multi-processor computer architecture, and more particularly to an invocation architecture for generally concurrent process resolution.
2. Description of the Related Art
A number of computer architectures supporting concurrent processing have been proposed.
In one kind of concurrent architecture, programs are compiled for a known, fixed configuration of processors and memory. These static systems use knowledge about the configuration of the system on which they are to be executed in order to compile their programs.
In other types of systems, a processor hierarchy designates one processor as a "master," on which a run-time operating system or kernel makes decisions as to which of the processor will execute parts of a process. Here again, the concurrency is predetermined in terms of location of execution and the programs are compiled accordingly.
Each of these systems suffers from drawbacks. Fixed configuration systems are unable to adapt to variations in existing programs and hardware. For example, a typical system has a fixed number of processors which is a power of two and which can only be increased by filed numbers of processors. When a system is reconfigured, existing programs usually have to be re-compiled to take advantage of the new configurations. None of the existing systems is able to provide for generally concurrent process resolution which can exploit as much expressed concurrency as possible while using available resources in a flexible, automatic, optimal and distributed manner. Such a generally concurrent architecture is desirable.